1. Field
An embodiment of the present invention relates to the field of integrated circuit testing and more particularly, to integrated circuit power supply noise modeling, simulation, and test pattern development.
2. Discussion of Related Art
With the increasing complexity and integration levels of integrated circuit devices, managing power dissipation while achieving high performance levels is an increasingly difficult challenge.
In this environment, with smaller dimensions, tight design windows and tight timing constraints, any variations in the power supply can be detrimental to the performance and/or functionality of an integrated circuit device. For example, where a lead integrated circuit product is first designed for a first process and then moved to a new, smaller geometry process, such issues may be even more pronounced. When moving an integrated circuit product to a smaller process, it is frequently the practice that major portions of the chip are not redesigned. Thus, for example, with the smaller geometry process, power supply lines become narrower, but there may not be a commensurate reduction in current demand. With variations in the power supply, some devices may be starved for power creating a speed path or malfunction.
Such power supply noise-related failures may be difficult to model, simulate and/or identify during testing using prior analysis and test tools.